In the BeiDou satellite synchronization system, FPGA-based solutions are typically used. However, using an ARM single-core system during scheduling can lead to resource contention and real-time response deviations. While ARM processors are superior to FPGA in handling business logic, floating-point calculations, and similar tasks, this paper proposes a solution for BeiDou 1PPS synchronization and timing based on ARM processors. The synchronization calculation is implemented using the least squares method combined with a sliding window, while the timing calculation is achieved through a phased growth mechanism. Additionally, a delay correction algorithm is introduced to address cycle boundary acquisition deviations caused by interrupt conflicts during signal processing. When the system detects that the data is about to overflow, the algorithm delays recording the rising edge signal′s cycle value and applies corrections. Experimental results show that this algorithm can achieve synchronization accuracy at the level of 10-8 s, proving its effectiveness in high-precision time synchronization applications.