In semantic communication, image semantic information processing heavily relies on computationally intensive convolutional neural networks, which require higher computational performance, especially when handling high-resolution images. This presents a significant challenge for the application of semantic communication in edge scenarios. To address this, this paper proposes an FPGA-based semantic information processing accelerator, which innovatively integrates the convolutional neural network encoder and rANS encoding in the same hardware accelerator. Specifically, the accelerator adopts a systolic array architecture combined with multiplyaccumulate units, loop tiling strategy, and a dual-buffer structure to fully leverage the parallel computing capabilities and on-chip storage resources of the FPGA, improving data transmission efficiency and computational performance. Each processing unit integrates multiple multiply-accumulate units, capable of performing two INT8 multiplications and local accumulation in each clock cycle. Finally, rANS is used for 8-way parallel encoding of the output features, further compressing the feature data. Experimental results show that, on the ZCU104 platform, the design achieves a throughput of 300.5 GOPS with a power efficiency of 66.77 GOPS/W when processing 1080P images, providing a processing speed approximately 6 times faster than Intel CPUs and 58 times faster than ARM CPUs. Compared with other FPGA accelerators, the BRAM efficiency improves by approximately 730%, 40%, and 63%, the energy efficiency by approximately 802%, 60% and 3%, and the DSP efficiency by approximately 476%, 70% and 133%. The proposed accelerator demonstrates significant performance advantages and can efficiently process image semantic information, offering broad practical application potential.